This invention relates to manufacture of insulated-gate field effect transistors, and more particularly to short-channel transistors having drain-to-channel interface made by the sidewall spacer method.
A high-performance insulated gate field effect transistor using oxide sidewall-spacer technology to provide a lightly-doped drain-to-channel interface is disclosed by Tsang et al in IEEE Journal of Solid-State Circuits, April 1982, p. 220. This structure is advantageous for short channel transistors as needed in VLSI devices such as 256K-bit or 1-Megabit memory chips, for example. Small geometry transistors introduce a variety of problems including short channel Vt effects, low breakdown voltage and hot carrier generation which produce substrate and gate currents. The oxide sidewall-spacer technology tends to avoid some of these effects by reducing the electric field at the drain end of the transistor. That is, the devices tend to reduce the effects of hot electrons associated with high electric fields at high implant concentration gradients (implant boundaries). Problems are introduced in fabrication to these devices, however, due to the etching process for creating the sidewall spacer. Also, the implant used to close the gap beneath the sidewall spacer results in a doping level higher than desired and the junction is not graded to the extent desired. Further, phosphorous can be unintentionally introduced from the multi-level insulator, and this produces a junction ahead of the arsenic-doped junction because phosphorous diffuses faster. Alternatives to the Tsang et al process were disclosed by Takeda et al at p. 245 of Journal of Solid State Circuits, April 1982, but none of these was suitable for high-performance dynamic RAMs. Arsenic is needed for the N+ source/drain regions so that the sheet resistance will be low. However, the arsenic implant previously used for the gap-closing implant is not acceptable because of the steep junction grading. This steep grading results in high electric fields which enhance impact ionization and hence produce high substrate and gate currents. The prior configuration also gives high overlap capacitance.
In prior application Ser. No. 412,753, filed Aug. 30, 1982 by Smayling and Duane, assigned to Texas Instruments and now U.S. Pat. No. 4,566,175, a lightly-doped drain transistor is disclosed which avoids some of the problems in the Tsang et al and the Takeda et al devices by using a fast diffusing (phosphorus) light implant and a slowly-diffusing (arsenic) heavy implant, both after the sidewall spacer is defined, so that the field gradients are reduced, yet the process is simplified. However, the control of phosphorus diffusion and sidewall sapcer length are critical in this process.
It is the principal object of this invention to provide improved short-channel MOS transistors for VLSI semiconductor devices, particularly made by a process of less critical control requirements. Another object is to provide an improved transistor employing oxide sidewall spacer technology. SUMMARY OF THE INVENTION
A transistor for VLSI devices made by the sidewall-spacer method uses a reach-through implant both before and after the sidewall spacer is defined. An arsenic implant self-aligned with the gate prior to the sidewall oxide, then a phosphorus implant and lateral diffusion performed after the sidewall oxide etch creates a reduced impurity concentration and graded junction for the reach-through implanted region beneath the oxide sidewall spacer. An arsenic implant after the sidewall spacer is in place provides the high concentration source/drain regions.